Line data    Source code

       1             : use crate::memory::memory_map::arm11_physical_memory_map::{
       2             :     ARM11_BOOTROM_SIZE, AXI_WRAM_MEMORY_RANGE, AXI_WRAM_MEMORY_SIZE, DSP_MEMORY_RANGE,
       3             :     DSP_MEMORY_SIZE, FCRAM_RANGE, FCRAM_SIZE, IO_MEMORY_RANGE, IO_MEMORY_SIZE,
       4             :     MPCORE_PRIVATE_MEMORY_RANGE, MPCORE_PRIVATE_MEMORY_SIZE, VRAM_RANGE, VRAM_SIZE,
       5             : };
       6             : use crate::memory::memory_map::arm9_physical_memory_map::ARM9_BOOTROM_SIZE;
       7             : 
       8             : /// The internal state of the [`MemoryBus`].
       9             : ///
      10             : /// Based on the described [`crate::memory::memory_map`] module which adapts the
      11             : /// [Nintendo 3DS - Memory Layout] documentation.
      12             : ///
      13             : /// [Nintendo 3DS - Memory Layout]: https://tinyurl.com/ukwyyfkv
      14             : pub struct MemoryBusState {
      15             :     // ARM11 specific memory
      16             :     /// The ARM11 BIOS boot ROM.
      17             :     arm11_bootrom: Box<[u8; ARM11_BOOTROM_SIZE]>,
      18             :     /// Memory region used to internally access the private MPCore peripherals,
      19             :     /// such as the Interrupt Distributor, the MP11 CPU interrupt interface, the
      20             :     /// Timers and Watchdog, and the Snoop Control Unit(SCU).
      21             :     /// See: <https://tinyurl.com/44pj4jps>.
      22             :     mpcore_private_memory: Box<[u8; MPCORE_PRIVATE_MEMORY_SIZE]>,
      23             : 
      24             :     // ARM9 specific memory
      25             :     /// The ARM9 BIOS boot ROM.
      26             :     arm9_bootram: Box<[u8; ARM9_BOOTROM_SIZE]>,
      27             : 
      28             :     // Shared memory
      29             :     /// Memory region used to access the I/O registers to control peripherals.
      30             :     io_memory: Box<[u8; IO_MEMORY_SIZE]>,
      31             :     vram: Box<[u8; VRAM_SIZE]>,
      32             :     dsp_memory: Box<[u8; DSP_MEMORY_SIZE]>,
      33             :     axi_wram: Box<[u8; AXI_WRAM_MEMORY_SIZE]>,
      34             :     fcram: Box<[u8; FCRAM_SIZE]>,
      35             : }
      36             : 
      37             : impl Default for MemoryBusState {
      38           0 :     fn default() -> Self {
      39           0 :         Self {
      40           0 :             arm11_bootrom: Box::new([0; ARM11_BOOTROM_SIZE]),
      41           0 :             mpcore_private_memory: Box::new([0; MPCORE_PRIVATE_MEMORY_SIZE]),
      42           0 :             arm9_bootram: Box::new([0; ARM9_BOOTROM_SIZE]),
      43           0 :             io_memory: Box::new([0; IO_MEMORY_SIZE]),
      44           0 :             vram: Box::new([0; VRAM_SIZE]),
      45           0 :             dsp_memory: Box::new([0; DSP_MEMORY_SIZE]),
      46           0 :             axi_wram: Box::new([0; AXI_WRAM_MEMORY_SIZE]),
      47           0 :             fcram: Box::new([0; FCRAM_SIZE]),
      48           0 :         }
      49           0 :     }
      50             : }
      51             : 
      52             : pub struct MemoryBus {}
      53             : 
      54             : /// Processors that can access the memory bus.
      55             : enum MemoryBusAccessor {
      56             :     /// The ARM9 processor.
      57             :     Arm9,
      58             :     /// The first ARM11 processor core.
      59             :     Arm11Core1,
      60             :     /// The second ARM11 processor core.
      61             :     Arm11Core2,
      62             : }
      63             : 
      64             : impl MemoryBus {
      65             :     //  pub fn read_byte()
      66             : }