Module eikon3ds_core::arch::register_specified_shift

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Utils for register specified shift operations, register specified meaning a shift amount that comes from a Risc CPU register. See: ARM7TDMI Datasheet Page.36-38

Register specified shift special effects list:

  1. If the shift amount is 0, the carry-out is the old carry flag and val is untouched.

  2. If the shift amount is between 1 and 31, it will operate the same as its instruction_specified_shift counter part.

  3. If the shift amount is 32 or more, there are side effects depending on the shift:

  • LSL by 32 has result zero, carry out equal to bit 0 of the val.

  • LSL by more than 32 has result zero, carry out zero.

  • LSR by 32 has result zero, carry out equal to bit 31 of the val.

  • LSR by more than 32 has result zero, carry out zero.

  • ASR by 32 or more has the shift results val filled with and carry out equal to bit 31 of the val.

  • ROR by 32 has result equal to Rm, carry out equal to bit 31 of the val.

  • ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the of range 1 to 32.

Functions

  • arithmetic_shift_right
    Shifts bits right by a register specified amount while preserving the sign of the val.
  • rotate_right
    Rotates bits right by a register specified amount.
  • shift_left
    Shifts bits left by a register specified amount.
  • shift_right
    Shifts bits right by a register specified amount.