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use crate::memory::memory_map::arm11_physical_memory_map::{
    ARM11_BOOTROM_SIZE, AXI_WRAM_MEMORY_RANGE, AXI_WRAM_MEMORY_SIZE, DSP_MEMORY_RANGE,
    DSP_MEMORY_SIZE, FCRAM_RANGE, FCRAM_SIZE, IO_MEMORY_RANGE, IO_MEMORY_SIZE,
    MPCORE_PRIVATE_MEMORY_RANGE, MPCORE_PRIVATE_MEMORY_SIZE, VRAM_RANGE, VRAM_SIZE,
};
use crate::memory::memory_map::arm9_physical_memory_map::ARM9_BOOTROM_SIZE;

/// The internal state of the [`MemoryBus`].
///
/// Based on the described [`crate::memory::memory_map`] module which adapts the
/// [Nintendo 3DS - Memory Layout] documentation.
///
/// [Nintendo 3DS - Memory Layout]: https://tinyurl.com/ukwyyfkv
pub struct MemoryBusState {
    // ARM11 specific memory
    /// The ARM11 BIOS boot ROM.
    arm11_bootrom: Box<[u8; ARM11_BOOTROM_SIZE]>,
    /// Memory region used to internally access the private MPCore peripherals,
    /// such as the Interrupt Distributor, the MP11 CPU interrupt interface, the
    /// Timers and Watchdog, and the Snoop Control Unit(SCU).
    /// See: <https://tinyurl.com/44pj4jps>.
    mpcore_private_memory: Box<[u8; MPCORE_PRIVATE_MEMORY_SIZE]>,

    // ARM9 specific memory
    /// The ARM9 BIOS boot ROM.
    arm9_bootram: Box<[u8; ARM9_BOOTROM_SIZE]>,

    // Shared memory
    /// Memory region used to access the I/O registers to control peripherals.
    io_memory: Box<[u8; IO_MEMORY_SIZE]>,
    vram: Box<[u8; VRAM_SIZE]>,
    dsp_memory: Box<[u8; DSP_MEMORY_SIZE]>,
    axi_wram: Box<[u8; AXI_WRAM_MEMORY_SIZE]>,
    fcram: Box<[u8; FCRAM_SIZE]>,
}

impl Default for MemoryBusState {
    fn default() -> Self {
        Self {
            arm11_bootrom: Box::new([0; ARM11_BOOTROM_SIZE]),
            mpcore_private_memory: Box::new([0; MPCORE_PRIVATE_MEMORY_SIZE]),
            arm9_bootram: Box::new([0; ARM9_BOOTROM_SIZE]),
            io_memory: Box::new([0; IO_MEMORY_SIZE]),
            vram: Box::new([0; VRAM_SIZE]),
            dsp_memory: Box::new([0; DSP_MEMORY_SIZE]),
            axi_wram: Box::new([0; AXI_WRAM_MEMORY_SIZE]),
            fcram: Box::new([0; FCRAM_SIZE]),
        }
    }
}

pub struct MemoryBus {}

/// Processors that can access the memory bus.
enum MemoryBusAccessor {
    /// The ARM9 processor.
    Arm9,
    /// The first ARM11 processor core.
    Arm11Core1,
    /// The second ARM11 processor core.
    Arm11Core2,
}

impl MemoryBus {
    //  pub fn read_byte()
}