Struct eikon3ds_core::cpu::registers::Cpsr

struct Cpsr {

    sign_flag: bool,
    zero_flag: bool,
    carry_flag: bool,
    overflow_flag: bool,
    sticky_overflow_flag: bool,
    jazelle_state: bool,
    greater_than_or_equal_to: [bool; 4],
    data_endianness_bit: bool,
    imprecise_data_abort: bool,
    irq_disabled: bool,
    fiq_disabled: bool,
    thumb_state: bool,
    mode: OperatingMode,
}

The current program status register.

Read more ARM9: https://tinyurl.com/2wxzw232.

Read more ARM11: https://tinyurl.com/ymcvpnme.

Fields

sign_flag: bool

Indicates if the result of a logical or arithmetic operation is negative.

zero_flag: bool

Indicates if the result of a logical or arithmetic operation is zero.

carry_flag: bool

Indicates if a arithmetic operation produced a carry, borrow, or the last bit of a shifted out value. This value is normally left unchanged by non-addition/subtraction operations, but there are exceptions for some.

overflow_flag: bool

Indicates if a arithmetic operation produced an overflow. This value is normally left unchanged by non-addition/subtraction operations, but there are exceptions for some.

sticky_overflow_flag: bool

Indicates if a overflow and/or saturation has occurred in some DSP-oriented instructions.

jazelle_state: bool

ARM11 only: Indicates if the processor is in Jazelle state to support execution of Java bytecode. The Nintendo 3DS does not support Jazelle, if the processor attempts to enter Jazelle using the BXJ instruction, it will function as a normal BX instruction. See: https://tinyurl.com/3y8aycz4.

greater_than_or_equal_to: [bool; 4]

ARM11 only: Set by SIMD instructions to indicate whether the result of a SIMD instruction is greater than or equal to the corresponding operand. Abbreviated as “GE” and composed of 4 bits, each bit corresponds to a halfword or byte in the result. These flags are later used to control a later SEL instruction.

For instructions that operate on halfwords:

• set or clear GE[3:2] together, based on the result on the top halfword calculation.
• set or clear GE[1:0] together, based on the result on the bottom halfword calculation.

For instructions that operate on bytes:

• set or clear GE[3] based on the result on the top byte calculation.
• set or clear GE[2] based on the result on the second byte calculation.
• set or clear GE[1] based on the result on the third byte calculation.
• set or clear GE[0] based on the result on the bottom byte calculation.

Using the rules above, each bit are set or cleared if the results of the corresponding calculation are as follows:

• for unsigned byte addition, if the result is greater than or equal to 2^8.
• for unsigned halfword addition, of the result is greater than or equal to 2^16.
• for unsigned subtraction, if the result is greater than or equal to zero.
• for signed arithmetic, if the result is greater than or equal to zero.

data_endianness_bit: bool

ARM11 only: Controls the endianness of load and store instructions. This bit is ignored by instruction fetches. When set, load/store operates in big-endian, when cleared, load/store operates in little-endian.

imprecise_data_abort: bool

ARM11 only: Indicates whether to disable imprecise Data Aborts.

irq_disabled: bool

Whether to disable IRQ interrupts.

fiq_disabled: bool

Whether to disable FIQ interrupts.

thumb_state: bool

Indicates if the processor is in THUMB when set or ARM state when cleared.

mode: OperatingMode

The operating mode the processor is currently in.

Implementations

impl Cpsr

const SIGN_FLAG_IDX: i32 = 31i32

const ZERO_FLAG_IDX: i32 = 30i32

const CARRY_FLAG_IDX: i32 = 29i32

const OVERFLOW_FLAG_IDX: i32 = 28i32

const STICKY_OVERFLOW_IDX: i32 = 27i32

const JAZELLE_STATE_IDX: i32 = 24i32

const GREATER_THAN_OR_EQUAL_TO_BIT_3_IDX: i32 = 22i32

const GREATER_THAN_OR_EQUAL_TO_BIT_2_IDX: i32 = 21i32

const GREATER_THAN_OR_EQUAL_TO_BIT_1_IDX: i32 = 20i32

const GREATER_THAN_OR_EQUAL_TO_BIT_0_IDX: i32 = 19i32

const E_BIT_IDX: i32 = 9i32

const A_BIT_IDX: i32 = 8i32

const IRQ_DISABLED_IDX: i32 = 7i32

const FIQ_DISABLED_IDX: i32 = 6i32

const THUMB_STATE_IDX: i32 = 5i32

const MODE_EXTRACT_BITS: u32 = 31u32

fn new() -> Self

fn get_mode(&self) -> OperatingMode

fn set(&mut self, val: u32)

Sets the value of the CPSR register.

Be aware that this function updates the CPSR mode value, but does not swap banked registers. Be sure to call Registers::switch_operating_mode along side this function to properly update the operating mode registers.

fn val(&self) -> u32

Trait Implementations

impl Reset for Cpsr

fn reset(&mut self)

Resets the CPSR register to its default state.

On reset, the CPSR enters OperatingMode::Supervisor and disabled data imprecise aborts, fiq, and irq bits. In our case, we will set all bits to false.

See: https://tinyurl.com/43kwv52u and https://tinyurl.com/2r9fmhyc.